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Reset, Stop, Mode Select, and Interrupt Timing
Table 19. Reset, Stop, Mode Select, and Interrupt Timing (continued)
No.
18
Characteristics
Delay from interrupt trigger to interrupt code
Expression
10 xT C + 5
Min
60.0
Max
Unit
ns
execution.
19
Duration of level sensitive IRQA assertion to
ensure interrupt service (when exiting Stop) 2, 3
? PLL is active during Stop and Stop delay is
enabled
9+(128K × T C)
704
—
us
(OMR Bit 6 = 0)
? PLL is active during Stop and Stop delay is not
25 × T C
138
—
ns
enabled
(OMR Bit 6 = 1)
? PLL is not active during Stop and Stop delay is
9+(128KxT C )+T lock
5.7
ms
enabled (OMR Bit 6 = 0)
? PLL is not active during Stop and Stop delay is
(25 x T C )+T lock
5
ms
not enabled (OMR Bit 6 = 1)
20
? Delay from IRQA, IRQB, IRQC, IRQD, NMI
10 x T C + 3.0
59.0
ns
assertion to general-purpose transfer output
valid caused by first interrupt instruction
execution
21
Interrupt Requests Rate
? ESAI, ESAI_1, SHI, DAX, Timer
? DMA
? IRQ, NMI (edge trigger)
? IRQ (level trigger)
12 x T C
8 x T C
8 x T C
12 c T C
—
—
—
—
—
—
—
—
ns
ns
ns
ns
22
DMA Requests Rate
? Data read from ESAI, ESAI_1, SHI, DAX
? Data write to ESAI, ESAI_1, SHI, DAX
? Timer
? IRQ, NMI (edge trigger)
6 x T C
7 x T C
2 x T C
3 x T C
—
—
—
—
—
—
—
—
ns
ns
ns
ns
Note:
1. When using fast interrupts and IRQA, IRQB, IRQC, and IRQD are defined as level-sensitive, timings 19 through 21 apply
to prevent multiple interrupt service. To avoid these timing restrictions, the deasserted Edge-triggered mode is
recommended when using fast interrupts. Long interrupts are recommended when using Level-sensitive mode.
2. For PLL disable, using external clock (PCTL Bit 13 = 0), no stabilization delay is required and recovery time will be
defined by the OMR Bit 6 settings.
For PLL enable, (if bit 12 of the PCTL register is 0), the PLL is shutdown during Stop. Recovering from Stop requires the
PLL to get locked. The PLL lock procedure duration, PLL Lock Cycles (PLC), may be in the range of 0.5 ms.
3. Periodically sampled and not 100% tested
4. RESET duration is measured during the time in which RESET is asserted, V DD is valid, and the EXTAL input is active and
valid. When the V DD is valid, but the other “required RESET duration” conditions (as specified above) have not been yet
met, the device circuitry will be in an uninitialized state that can result in significant power consumption and heat-up.
Designs should minimize this state to the shortest possible duration.
DSP56371 Data Sheet, Rev. 4.1
Freescale Semiconductor
39
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